一.ACPI共有六种状态复习
G3—主机板上只有电池供电；
S0--实际上这就是我们平常的工作状态，所有设备全开，功耗一般会超过80W；
S1--也称为POS（Power on Suspend），这时除了通过CPU时钟控制器将CPU关闭之外，其他的部件仍然正常工作，这时的功耗一般在30W以下；（其实有些CPU降温软体就是利用这种工作原理）
S3--这就是我们熟悉的STR（Suspend to RAM），这时的功耗不超过10W；
S4--也称为STD（Suspend to Disk），这时系统主电源关闭，但是硬碟仍然带电并可以被唤醒；
S5--这种状态是最乾脆的，就是连电源在内的所有设备全部关闭，功耗为0。
我们最常用到的是S3状态，即Suspend to RAM（挂起到记忆体）状态，简称STR。顾名思义，STR就是把系统进入STR前的工作状态资料都存放到记忆体中去。在STR状态下，电源仍然继续为记忆体等最必要的设备供电，以确保资料不丢失，而其他设备均处於关闭状态，系统的耗电量极低。一旦我们按下Power按钮（主机电源开关），系统就被唤醒，马上从记忆体中读取资料并恢复到STR之前的工作状态。记忆体的读写速度极快，因此我们感到进入和离开STR状态所花费的时间不过是几秒钟而已；而S4状态，即STD（挂起到硬碟）与STR的原理是完全一样的，只不过资料是保存在硬碟中。由於硬碟的读写速度比记忆体要慢得多，因此用起来也就没有STR那麼快了。STD的优点是只通过软体就能实现，比如Windows 2000就能在不支援STR的硬体上实现STD。
二.G3 S5时序
1. G3：表示主机板还没有插上ATX POWER 的状态。主机板上只有电池供电
S5：表示主机板有插上ATX POWER，但没有按下power button的状态.此时主机板上有5VSB和电池供电
相关联信号脚的描述
name
description
VCCRTC
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not expected to be shut off unless the RTC battery is removed or completely drained.
NOTE:Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an ICH6-based platform can be done by using a jumper on RTCRST# or GPI.
RTCRST#
RTC Reset:When asserted, this signal resets register bits in the RTC well.NOTES:1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on.2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the RSMRST# pin.
V5REF_SUS
Reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations.
VCCSUS3_3
3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations.
VCCSUS1_5
1.5 V supply for resume well logic (3 pin). This power is not expected to be shut off unless the system is unplugged in desktop configurations or the main battery is removed or completely drained and AC power is not available in mobile configurations.This voltage may be generated internally (see Section 2.22.1 for strapping option). If generated internally, these pins should not be connected to an external supply.
LAN_RST#
LAN Reset:When asserted, the internal LAN controller will be put into reset. This signal must be asserted for at least 10 ms after the resume well power (VccSus3_3 and VccSus1_5 in desktop and VccLAN3_3 and VccLAN1_5 in mobile) is valid. When de-asserted, this signal is an indication that the resume (LAN for mobile) well power is stable.
NOTE:LAN_RST# must de-assert at some point to complete ICH6 power up sequencing.
RSMRST#
Resume Well Reset:This signal is used for resetting the resume power plane logic.
2.电池的作用：
1)破解BIOS密码的好招
2)CMOS放电
目前的主机板大多数使用纽扣电池为BIOS提供电力，也就是说，如果没有电，它里面的资讯就会丢失了。当它再次通上电时，BIOS就会回到未设置的原始状态，当然BIOS密码也就没有了。
3) BIOS与CMOS
BIOS是软体，CMOS是硬体，简单说CMOS是BIOS的载体
BIOS，完整地说应该是ROM－BIOS，是唯读记忆体基本输入／输出系统的缩写，它实际上是被固化到微机主机板ROM晶片上的一组程式，主要保存著有关微机系统最重要的基本输入输出程式，系统资讯设置、开机上电自检程式和系统启动程式等；为电脑提供最低级的、最直接的硬体控制。准确地说， BIOS是硬体与软体程式之间的一个“转换器”或者说是介面(虽然它本身也只是一个程式)，负责解决硬体的即时需求，并按软体对硬体的操作要求具体执行。 BIOS ROM 晶片不但可以在主机板上看到，而且BIOS管理功能如何在很大程度上决定了主机板性能是否优越。
CMOS-------互补金属氧化物半导体
CMOS的用处很多，比如有的数码相机的感光器就是用CMOS的。CMOS是互补金属氧化物半导体的缩写。其本意是指制造大型积体电路晶片用的 一种技术或用这种技术制造出来的晶片。在这里通常是指微机主机板上的一块可读写的RAM晶片。它存储了微机系统的实时钟资讯和硬体设定资讯等，共计128个 位元组。系统在加电引导机器时，要读取CMOS资讯，用来初始化机器各个部件的状态。它靠系统电源和後备电池来供电，系统掉电後其资讯不会丢失。
BIOS和CMOS的作用和区别
而BIOS是基本输入输出系统的缩写，指集成在主机板上的一个ROM晶片，其中保存了微机系统最重要的基本输入输出程式、系统开机自检程式等。它负责开机时，对系统各项硬体进行初始化设置和测试，以保证系统能够正常工作。由於CMOS与BIOS都跟微机系统设置密切相关，所以才有CMOS设置和 BIOS设置的说法。CMOS RAM是系统参数存放的地方，而BIOS中系统设置程式是完成参数设置的手段。因此，准确的说法应是通过BIOS设置程式对CMOS参数进行设置。而我们 平常所说的CMOS设置和BIOS设置是其简化说法，也就在一定程度上造成了两个概念的混淆。
3.VCCRTC的作用
电路如下：
VCCRTC供电用来保存CMOS设置中的资料不丢.
三. S5 S0时序
按下Power Button ,PWRBT- 讯号由High ->Low 触发I/O chip,I/O chip 送出LED-BLK 为High 0.7v,使PS-ON 被拉Low 系统开机，其过程如下
一.G3 state S0 state
G3:主机板上没有其他任何电源供电，只有电池供电
S0:开机状态，所有设奋处於全开状态
时序如下图：
SUSCLKO:This clock is an output of the RTC generator circuit to use by other chips for refresh clock.
PWROKI:When asserted, PWROK is an indication to the ICH8 that all power rails have been stable for 99 ms and that PCICLK has been
stable for 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH8 asserts PLTRST#.
NOTE:PWROK must deassert for a minimum of three RTC clock periods in order for the ICH8 to fully reset the power and properly generate the PLTRST# output
VRMPWRGDI:This signal should be connected to be the processor’s VRM Power Good signifying the VRM is stable. This signal is
internally ANDed with the PWROK input. This signal is in the resume well.
SUS_STAT#O:This signal is asserted by the ICH8 to indicate that the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC interface.
PLTRST#O:The Intel® ICH8 asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, (G)MCH, TPM, etc.). The ICH8
asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The ICH8 drives PLTRST# inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. The ICH8 drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h).
NOTE:PLTRST# is in the VccSus3_3 well.
CPUSLP#O:This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during
that time, no snoops occur. The Intel® ICH8 can optionally assert the CPUSLP# signal when going to the S1 state.
STPCLK#O:STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH8 in response to one of many
hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock.
二.S0 state S5 state
时序如下图：
