数字集成电路设计:从VLSI体系结构到CMOS制造(英文版)(图灵原版电子与电气工程系列)(Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication)

基本信息·出版社：人民邮电出版社

·页码：845 页

·出版日期：2010年05月

·ISBN：9787115223586

·条形码：9787115223586

·版本：第1版

·装帧：平装

·开本：16

·正文语种：英语

·丛书名：图灵原版电子与电气工程系列

·外文书名：Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication

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内容简介本书从架构与算法讲起，介绍了功能验证、VHDL建模、同步电路设计、异步数据获娶能耗与散热、信号完整性、物理设计、设计验证等必备技术，还讲解了VLSI经济运作与项目管理，并简单阐释了CMOS技术的基础知识，全面覆盖了数字集成电路的整个设计开发过程。 本书既可作为高等院校微电子、电子技术等相关专业高年级师生和研究生的参考教材，也可供半导体行业工程师参考。

目录

目录 Chapter 1Introduction to Microelectronics1 1.1Economic impact1 1.2Concepts and terminology4 1.2.1The Guinness book of records point of view4 1.2.2The marketing point of view5 1.2.3The fabrication point of view6 1.2.4The design engineer's point of view10 1.2.5The business point of view17 1.3Design flow in digital VLSI18 1.3.1The Y-chart, a map of digital electronic systems18 1.3.2Major stages in VLSI design19 1.3.3Cell libraries28 1.3.4Electronic design automation software29 1.4Field-programmable logic30 1.4.1Configuration technologies30 1.4.2Organization of hardware resources32 1.4.3Commercial products35 1.5Problems37 1.6Appendix I: A brief glossary of logic families38 1.7Appendix II: An illustrated glossary of circuit-related terms40 Chapter 2From Algorithms to Architectures44 2.1The goals of architecture design44 2.1.1Agenda45 2.2The architectural antipodes45 2.2.1What makes an algorithm suitable for a dedicated VLSI architecture?50 2.2.2There is plenty of land between the architectural antipodes53 2.2.3Assemblies of general-purpose and dedicated processing units54 2.2.4Coprocessors55 2.2.5Application-specific instruction set processors55 2.2.6Configurable computing58 2.2.7Extendable instruction set processors59 2.2.8Digest60 2.3 Atransform approach to VLSI architecture design61 2.3.1There is room for remodelling in the algorithmic domain 62 2.3.2...and there is room in the architectural domain64 2.3.3Systems engineers and VLSI designers must collaborate64 2.3.4A graph-based formalism for describing processing algorithms65 2.3.5The isomorphic architecture66 2.3.6Relative merits of architectural alternatives67 2.3.7Computation cycle versus clock period69 2.4Equivalence transforms for combinational computations70 2.4.1Common assumptions71 2.4.2Iterative decomposition72 2.4.3Pipelining75 2.4.4Replication79 2.4.5Time sharing81 2.4.6Associativity transform86 2.4.7Other algebraic transforms87 2.4.8Digest87 2.5Options for temporary storage of data89 2.5.1Data access patterns89 2.5.2Available memory configurations and area occupation89 2.5.3Storage capacities90 2.5.4Wiring and the costs of going off-chip91 2.5.5Latency and timing91 2.5.6Digest92 2.6Equivalence transforms for nonrecursive computations93 2.6.1Retiming94 2.6.2Pipelining revisited95 2.6.3Systolic conversion97 2.6.4Iterative decomposition and time-sharing revisited98 2.6.5Replication revisited98 2.6.6Digest99 2.7Equivalence transforms for recursive computations99 2.7.1The feedback bottleneck100 2.7.2Unfolding of first-order loops101 2.7.3Higher-order loops103 2.7.4Time-variant loops105 2.7.5Nonlinear or general loops106 2.7.6Pipeline interleaving is not an equivalence transform109 2.7.7Digest111 2.8Generalizations of the transform approach112 2.8.1Generalization to other levels of detail112 2.8.2Bit-serial architectures113 2.8.3Distributed arithmetic116 2.8.4Generalization to other algebraic structures118 2.8.5Digest121 2.9Conclusions122 2.9.1Summary122 2.9.2The grand architectural alternatives from an energy point of view124 2.9.3A guide to evaluating architectural alternatives126 2.10Problems128 2.11Appendix I: A brief glossary of algebraic structures130 2.12Appendix II: Area and delay figures of VLSI subfunctions133 Chapter 3Functional Verification136 3.1How to establish valid functional specifications137 3.1.1Formal specification138 3.1.2Rapid prototyping138 3.2Developing an adequate simulation strategy139 3.2.1What does it take to uncover a design flaw during simulation?139 3.2.2Stimulation and response checking must occur automatically140 3.2.3Exhaustive verification remains an elusive goal142 3.2.4All partial verification techniques have their pitfalls143 3.2.5Collecting test cases from multiple sources helps150 3.2.6Assertion-based verification helps150 3.2.7Separating test development from circuit design helps151 3.2.8Virtual prototypes help to generate expected responses153 3.3Reusing the same functional gauge throughout the entire design cycle153 3.3.1Alternative ways to handle stimuli and expected responses155 3.3.2Modular testbench design156 3.3.3A well-defined schedule for stimuli and responses156 3.3.4Trimming run times by skipping redundant simulation sequences159 3.3.5Abstracting to higher-level transactions on higher-level data160 3.3.6Absorbing latency variations across multiple circuit models164 3.4Conclusions166 3.5Problems168 3.6Appendix I: Formal approaches to functional verification170 3.7Appendix II: Deriving a coherent schedule for simulation and test171 Chapter 4Modelling Hardware with VHDL175 4.1Motivation175 4.1.1Why hardware synthesis?175 4.1.2What are the alternatives to VHDL?176 4.1.3What are the origins and aspirations of the IEEE 1076 standard?176 4.1.4Why bother learning hardware description languages?179 4.1.5Agenda180 4.2Key concepts and constructs of VHDL180 4.2.1Circuit hierarchy and connectivity181 4.2.2Concurrent processes and process interaction185 4.2.3A discrete replacement for electrical signals192 4.2.4An event-based concept of time for governing simulation200 4.2.5Facilities for model parametrization211 4.2.6Concepts borrowed from programming languages216 4.3Putting VHDL to service for hardware synthesis223 4.3.1Synthesis overview223 4.3.2Data types224 4.3.3Registers, finite state machines, and other sequential subcircuits225 4.3.4RAMs, ROMs, and other macrocells231 4.3.5Circuits that must be controlled at the netlist level233 4.3.6Timing constraints234 4.3.7Limitations and caveats for synthesis238 4.3.8How to establish a register transfer-level model step by step238 4.4Putting VHDL to service for hardware simulation242 4.4.1Ingredients of digital simulation242 4.4.2Anatomy of a generic testbench242 4.4.3Adapting to a design problem at hand245 4.4.4The VITAL modelling standard IEEE 1076.4245 4.5Conclusions247 4.6Problems248 4.7Appendix I: Books and Web Pages on VHDL250 4.8Appendix II: Related extensions and standards251 4.8.1Protected shared variables IEEE 1076a251 4.8.2The analog and mixed-signal extension IEEE 1076.1252 4.8.3Mathematical packages for real and complex numbers IEEE 1076.2253 4.8.4The arithmetic packages IEEE 1076.3254 4.8.5A language subset earmarked for synthesis IEEE 1076.6254 4.8.6The standard delay format (SDF) IEEE 1497254 4.8.7A handy compilation of type conversion functions255 4.9Appendix III: Examples of VHDL models256 4.9.1Combinational circuit models256 4.9.2Mealy, Moore, and Medvedev machines261 4.9.3State reduction and state encoding268 4.9.4Simulation testbenches270 4.9.5Working with VHDL tools from different vendors285 Chapter 5The Case for Synchronous Design286 5.1Introduction286 5.2The grand alternatives for regulating state changes287 5.2.1Synchronous clocking287 5.2.2Asynchronous clocking288 5.2.3Self-timed clocking288 5.3Why a rigorous approach to clocking is essential in VLSI290 5.3.1The perils of hazards290 5.3.2The pros and cons of synchronous clocking291 5.3.3Clock-as-clock-can is not an option in VLSI293 5.3.4Fully self-timed clocking is not normally an option either294 5.3.5Hybrid approaches to system clocking294 5.4The dos and don’ts of synchronous circuit design296 5.4.1First guiding principle: Dissociate signal classes!296 5.4.2Second guiding principle: Allow circuits to settle before clocking!298 5.4.3Synchronous design rules at a more detailed level298 5.5Conclusions306 5.6Problems306 5.7Appendix: On identifying signals307 5.7.1Signal class307 5.7.2Active level308 5.7.3Signaling waveforms309 5.7.4Three-state capability 311 5.7.5Inputs, outputs, and bidirectional terminals311 5.7.6Present state vs. next state312 5.7.7Syntactical conventions312 5.7.8A note on upper- and lower-case letters in VHDL313 5.7.9A note on the portability of names across EDA platforms314 Chapter 6Clocking of Synchronous Circuits315 6.1What is the difficulty in clock distribution?315 6.1.1Agenda316 6.1.2Timing quantities related to clock distribution317 6.2How much skew and jitter does a circuit tolerate?317 6.2.1Basics 317 6.2.2Single-edge-triggered one-phase clocking319 6.2.3Dual-edge-triggered one-phase clocking326 6.2.4Symmetric level-sensitive two-phase clocking327 6.2.5Unsymmetric level-sensitive two-phase clocking331 6.2.6Single-wire level-sensitive two-phase clocking334 6.2.7Level-sensitive one-phase clocking and wave pipelining336 6.3How to keep clock skew within tight bounds339 6.3.1Clock waveforms339 6.3.2Collective clock buffers340 6.3.3Distributed clock buffer trees343 6.3.4Hybrid clock distribution networks344 6.3.5Clock skew analysis345 6.4How to achieve friendly input/output timing346 6.4.1Friendly as opposed to unfriendly I/O timing346 6.4.2Impact of clock distribution delay on I/O timing347 6.4.3Impact of PTV variations on I/O timing349 6.4.4Registered inputs and outputs350 6.4.5Adding artificial contamination delay to data inputs350 6.4.6Driving input registers from an early clock351 6.4.7Tapping a domain’s clock from the slowest component therein351 6.4.8癦ero-delay” clock distribution by way of a DLL or PLL352 6.5How to implement clock gating properly353 6.5.1Traditional feedback-type registers with enable353 6.5.2A crude and unsafe approach to clock gating354 6.5.3A simple clock gating scheme that may work under certain conditions355 6.5.4Safe clock gating schemes355 6.6Summary357 6.7Problems361 Chapter 7Acquisition of Asynchronous Data364 7.1Motivation364 7.2The data consistency problem of vectored acquisition366 7.2.1Plain bit-parallel synchronization366 7.2.2Unit-distance coding367 7.2.3Suppression of crossover patterns368 7.2.4Handshaking369 7.2.5Partial handshaking371 7.3The data consistency problem of scalar acquisition373 7.3.1No synchronization whatsoever373 7.3.2Synchronization at multiple places373 7.3.3Synchronization at a single place373 7.3.4Synchronization from a slow clock374 7.4Metastable synchronizer behavior374 7.4.1Marginal triggering and how it becomes manifest374 7.4.2Repercussions on circuit functioning378 7.4.3A statistical model for estimating synchronizer reliability379 7.4.4Plesiochronous interfaces381 7.4.5Containment of metastable behavior381 7.5Summary384 7.6Problems384 Chapter 8Gate- and Transistor-Level Design386 8.1CMOS logic gates386 8.1.1The MOSFET as a switch387 8.1.2The inverter388 8.1.3Simple CMOS gates396 8.1.4Composite or complex gates399 8.1.5Gates with high-impedance capabilities403 8.1.6Parity gates406 8.1.7Adder slices407 8.2CMOS bistables409 8.2.1Latches410 8.2.2Function latches412 8.2.3Single-edge-triggered flip-flops413 8.2.4The mother of all flip-flops415 8.2.5Dual-edge-triggered flip-flops417 8.2.6Digest418 8.3CMOS on-chip memories418 8.3.1Static RAM418 8.3.2Dynamic RAM423 8.3.3Other differences and commonalities424 8.4Electrical CMOS contraptions425 8.4.1Snapper425 8.4.2Schmitt trigger426 8.4.3Tie-off cells427 8.4.4Filler cell or fillcap428 8.4.5Level shifters and input/output buffers429 8.4.6Digitally adjustable delay lines429 8.5Pitfalls430 8.5.1Busses and three-state nodes430 8.5.2Transmission gates and other bidirectional components434 8.5.3What do we mean by safe design?437 8.5.4Microprocessor interface circuits438 8.5.5Mechanical contacts440 8.5.6Conclusions440 8.6Problems442 8.7Appendix I: Summary on electrical MOSFET models445 8.7.1Naming and counting conventions445 8.7.2The Sah model446 8.7.3The Shichman–Hodges model450 8.7.4The alpha-power-law model450 8.7.5Second-order effects452 8.7.6Effects not normally captured by transistor models455 8.7.7Conclusions456 8.8Appendix II: The Bipolar Junction Transistor457 Chapter 9Energy Efficiency and Heat Removal459 9.1What does energy get dissipated for in CMOS circuits?459 9.1.1Charging and discharging of capacitive loads460 9.1.2Crossover currents465 9.1.3Resistive loads467 9.1.4Leakage currents468 9.1.5Total energy dissipation470 9.1.6CMOS voltage scaling471 9.2How to improve energy efficiency474 9.2.1General guidelines474 9.2.2How to reduce dynamic dissipation476 9.2.3How to counteract leakage482 9.3Heat flow and heat removal488 9.4Appendix I: Contributions to node capacitance490 9.5Appendix II: Unorthodox approaches491 9.5.1Subthreshold logic491 9.5.2Voltage-swing-reduction techniques492 9.5.3Adiabatic logic492 Chapter 10Signal Integrity495 10.1Introduction495 10.1.1How does noise enter electronic circuits?495 10.1.2How does noise affect digital circuits?496 10.1.3Agenda499 10.2Crosstalk499 10.3Ground bounce and supply droop499 10.3.1Coupling mechanisms due to common series impedances499 10.3.2Where do large switching currents originate?501 10.3.3How severe is the impact of ground bounce?501 10.4How to mitigate ground bounce504 10.4.1Reduce effective series impedances505 10.4.2Separate polluters from potential victims510 10.4.3Avoid excessive switching currents513 10.4.4Safeguard noise margins517 10.5Conclusions519 10.6Problems519 10.7Appendix: Derivation of second-order approximation521 Chapter 11Physical Design523 11.1Agenda523 11.2Conducting layers and their characteristics523 11.2.1Geometric properties and layout rules523 11.2.2Electrical properties527 11.2.3Connecting between layers527 11.2.4Typical roles of conducting layers529 11.3Cell-based back-end design531 11.3.1Floorplanning531 11.3.2Identify major building blocks and clock domains532 11.3.3Establish a pin budget533 11.3.4Find a relative arrangement of all major building blocks534 11.3.5Plan power, clock, and signal distribution535 11.3.6Place and route (P&R)538 11.3.7Chip assembly539 11.4Packaging540 11.4.1Wafer sorting543 11.4.2Wafer testing543 11.4.3Backgrinding and singulation544 11.4.4Encapsulation544 11.4.5Final testing and binning544 11.4.6Bonding diagram and bonding rules545 11.4.7Advanced packaging techniques546 11.4.8Selecting a packaging technique551 11.5Layout at the detail level551 11.5.1Objectives of manual layout design552 11.5.2Layout design is no WYSIWYG business552 11.5.3Standard cell layout556 11.5.4Sea-of-gates macro layout559 11.5.5SRAM cell layout559 11.5.6Lithography-friendly layouts help improve fabrication yield561 11.5.7The mesh, a highly efficient and popular layout arrangement562 11.6Preventing electrical overstress562 11.6.1Electromigration562 11.6.2Electrostatic discharge565 11.6.3Latch-up571 11.7Problems575 11.8Appendix I: Geometric quantities advertized in VLSI576 11.9Appendix II: On coding diffusion areas in layout drawings577 11.10Appendix III: Sheet resistance579 Chapter 12Design Verification581 12.1Uncovering timing problems581 12.1.1What does simulation tell us about timing problems?581 12.1.2How does timing verification help?585 12.2How accurate are timing data?587 12.2.1Cell delays588 12.2.2Interconnect delays and layout parasitics593 12.2.3Making realistic assumptions is the point597 12.3More static verification techniques598 12.3.1Electrical rule check598 12.3.2Code inspection599 12.4Post-layout design verification601 12.4.1Design rule check602 12.4.2Manufacturability analysis604 12.4.3Layout extraction605 12.4.4Layout versus schematic605 12.4.5Equivalence checking 606 12.4.6Post-layout timing verification606 12.4.7Power grid analysis607 12.4.8Signal integrity analysis607 12.4.9Post-layout simulations607 12.4.10The overall picture607 12.5Conclusions608 12.6Problems609 12.7Appendix I: Cell and library characterization611 12.8Appendix II: Equivalent circuits for interconnect modelling612 Chapter 13VLSI Economics and Project Management615 13.1Agenda615 13.2Models of industrial cooperation617 13.2.1Systems assembled from standard parts exclusively617 13.2.2Systems built around program-controlled processors618 13.2.3Systems designed on the basis of field-programmable logic619 13.2.4Systems designed on the basis of semi-custom ASICs620 13.2.5Systems designed on the basis of full-custom ASICs622 13.3Interfacing within the ASIC industry623 13.3.1Handoff points for IC design data623 13.3.2Scopes of IC manufacturing services624 13.4Virtual components627 13.4.1Copyright protection vs. customer information627 13.4.2Design reuse demands better quality and more thorough verification628 13.4.3Many existing virtual components need to be reworked629 13.4.4Virtual components require follow-up services629 13.4.5Indemnification provisions630 13.4.6Deliverables of a comprehensive VC package630 13.4.7Business models631 13.5The costs of integrated circuits632 13.5.1The impact of circuit size633 13.5.2The impact of the fabrication process636 13.5.3The impact of volume638 13.5.4The impact of configurability639 13.5.5Digest640 13.6Fabrication avenues for small quantities642 13.6.1Multi-project wafers642 13.6.2Multi-layer reticles643 13.6.3Electron beam lithography643 13.6.4Laser programming643 13.6.5Hardwired FPGAs and structured ASICs644 13.6.6Cost trading644 13.7The market side645 13.7.1Ingredients of commercial success645 13.7.2Commercialization stages and market priorities646 13.7.3Service versus product649 13.7.4Product grading650 13.8Making a choice651 13.8.1ASICs yes or no?651 13.8.2Which implementation technique should one adopt?655 13.8.3What if nothing is known for sure?657 13.8.4Can system houses afford to ignore microelectronics?658 13.9Keys to successful VLSI design660 13.9.1Project definition and marketing660 13.9.2Technical management661 13.9.3Engineering662 13.9.4Verification665 13.9.5Myths665 13.10Appendix: Doing business in microelectronics667 13.10.1Checklists for evaluating business partners and design kits667 13.10.2Virtual component providers669 13.10.3Selected low-volume providers669 13.10.4Cost estimation helps669 Chapter 14A Primer on CMOS Technology671 14.1The essence of MOS device physics671 14.1.1Energy bands and electrical conduction671 14.1.2Doping of semiconductor materials672 14.1.3Junctions, contacts, and diodes674 14.1.4MOSFETs676 14.2Basic CMOS fabrication flow682 14.2.1Key characteristics of CMOS technology682 14.2.2Front-end-of-line fabrication steps685 14.2.3Back-end-of-line fabrication steps688 14.2.4Process monitoring689 14.2.5Photolithography689 14.3Variations on the theme697 14.3.1Copper has replaced aluminum as interconnect material697 14.3.2Low-permittivity interlevel dielectrics are replacing silicon dioxide698 14.3.3High-permittivity gate dielectrics to replace silicon dioxide699 14.3.4Strained silicon and SiGe technology701 14.3.5Metal gates bound to come back702 14.3.6Silicon-on-insulator (SOI) technology703 Chapter 15Outlook706 15.1Evolution paths for CMOS technology706 15.1.1Classic device scaling706 15.1.2The search for new device topologies709 15.1.3Vertical integration711 15.1.4The search for better semiconductor materials712 15.2Is there life after CMOS?714 15.2.1Non-CMOS data storage715 15.2.2Non-CMOS data processing716 15.3Technology push719 15.3.1The so-called industry “laws” and the forces behind them719 15.3.2Industrial roadmaps721 15.4Market pull723 15.5Evolution paths for design methodology724 15.5.1The productivity problem724 15.5.2Fresh approaches to architecture design727 15.6Summary729 15.7Six grand challenges730 15.8Appendix: Non-semiconductor storage technologies for comparison731 Appendix AElementary Digital Electronics732 A.1Introduction732 A.1.1Common number representation schemes732 A.1.2Notational conventions for two-valued logic734 A.2Theoretical background of combinational logic735 A.2.1Truth table735 A.2.2The n-cube736 A.2.3Karnaugh map736 A.2.4Program code and other formal languages736 A.2.5Logic equations737 A.2.6Two-level logic738 A.2.7Multilevel logic 740 A.2.8Symmetric and monotone functions741 A.2.9Threshold functions741 A.2.10Complete gate sets742 A.2.11Multi-output functions742 A.2.12Logic minimization743 A.3Circuit alternatives for implementing combinational logic747 A.3.1Random logic747 A.3.2Programmable logic array (PLA)747 A.3.3Read-only memory (ROM)749 A.3.4Array multiplier749 A.3.5Digest750 A.4Bistables and other memory circuits751 A.4.1Flip-flops or edge-triggered bistables752 A.4.2Latches or level-sensitive bistables755 A.4.3Unclocked bistables756 A.4.4Random access memories (RAMs)760 A.5Transient behavior of logic circuits761 A.5.1Glitches, a phenomenological perspective762 A.5.2Function hazards, a circuit-independent mechanism763 A.5.3Logic hazards, a circuit-dependent mechanism764 A.5.4Digest765 A.6Timing quantities766 A.6.1Delay quantities apply to combinational and sequential circuits766 A.6.2Timing conditions apply to sequential circuits only768 A.6.3Secondary timing quantities770 A.6.4Timing constraints address synthesis needs771 A.7Microprocessor input/output transfer protocols771 A.8Summary773 Appendix BFinite State Machines775 B.1Abstract automata775 B.1.1Mealy machine776 B.1.2Moore machine777 B.1.3Medvedev machine778 B.1.4Relationships between finite state machine models779 B.1.5Taxonomy of finite state machines782 B.1.6State reduction783 B.2Practical aspects and implementation issues785 B.2.1Parasitic states and symbols785 B.2.2Mealy-, Moore-, Medvedev-type, and combinational output bits787 B.2.3Through paths and logic instability787 B.2.4Switching hazards789 B.2.5Hardware costs790 B.3Summary793 Appendix CVLSI Designer’s Checklist794 C.1Design data sanity794 C.2Pre-synthesis design verification794 C.3Clocking795 C.4Gate-level considerations796 C.5Design for test797 C.6Electrical considerations798 C.7Pre-layout design verification799 C.8Physical considerations800 C.9Post-layout design verification800 C.10Preparation for testing of fabricated prototypes801 C.11Thermal considerations802 C.12Board-level operation and testing802 C.13Documentation802 Appendix DSymbols and constants804 D.1Mathematical symbols used804 D.2Abbreviations807 D.3Physical and material constants808 References811 Index832

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