计算机系统体系结构(第3版)
分類: 图书,计算机/网络,计算机理论,
作者： M.Morris Mano著
出 版 社： 清华大学出版社
出版时间： 1998-5-1字数：版次： 3页数： 523印刷时间： 19980501开本：印次：纸张：I S B N ： 9787302028314包装： 平装内容简介
本书介绍计算机体系结构以及计算机组织与设计，向读者提供掌握计算机硬件操作所必需的基本知识。内容包括：用于计算机组织和设计的各种部件；设计一台计算机的详细步骤：中央处理机，输入/输出及存储器的组织与体系结构；多处理概念。全书分13章：1.数字逻辑电路，2.数字部件。3.数据表示法，4.寄存器传输与微操作，5.基本计算机组织与设计，6.基本计算机的程序设计，7.微程序控制，8.中央处理机，9.流水处理与向量处理，10.计算机体系结构，11.输入/输出组织，12.存储器组织，13.多处理机。本书可作电气工程，计算机工程或计算机科学系的“计算机硬件系统”课的教材，还可作工程技术及科研人员了解计算机硬件体系结构基本知识的自学参考书。
目录
CHAPTER ONE Digital Logic Circuits
1-1 Digtal Computers
1-2 Logic Gates
1-3 Boolean Algebra
Complement of a Function
1-4 Map Simplification
Product-of-Sums Simplification
Don’t-Care Conditions
1-5 Combinational Circuits
Half-Adder
Full-Adder
1-6 Flip-Flops
SR Flip-Flops
D Flip-Flops
JK Flip-Flops
T Flip-Flops
Edge-Triggered Flip-Flops
Exctiation Tables
1-7 Sequential Circuits
Flip-Flops Input Equations
State Table
State Diagram
Design Example
Design Procedure
Problems
References
CHAPTER TWO Digital Components
2-1 Integrated Circuits
2-2 Decoders
NAND Gate Decoder
Decoder Expansion
Encoders
2-3 Multiplexers
2-4 Registers
Register with Parallel Load
2-5 Shift Registers
Bidirectional Shift Register with Parallel Load
2-6 Binary Counters
Binary Counters with Parallel Load
2-7 Memory Unit
Random-Access Memory
Read-Only Memory
Types of ROMs
Problems
References
CHAPTER THREE Data Representation
3-1 Data Types
Number Systems
Octal and Hexadecimal Numbers
Decimal Representation
Alphanumeric Representation
3-2 Complements
(r-1)’s Complement
(r’s) Complement
Subtraction of Unsigned Numbers
3-3 Fixed-Point Representation
Integer Representation
Arithmetic Addition
Arithmetic Subtraction
Overflow
Decimal Fixed-Point Representation
3-4 Floating-Point Representation
3-5 Other Binary Codes
Gray Code
Other Decimal Codes
Other Alphanumeric Codes
3-6 Error Detection Codes
Problems
References
CHAPTER FOUR Register Transfer and Microoperations
4-1 Register Transfer Language
4-2 Register Transfer
4-3 Bus and Memory Transfers
Three-State Bus Buffers
Memory Transfer
4-4 Arithmetic Microoperations
Binary Adder
Binary Adder-Subtractor
Binary Incrementer
Arithmetic Circuit
4-5 Logic Microoperations
List of Logic Microoperations
Hardware Implementation
Some Applications
4-6 Shift Microoperations
Hardware Implementation
4-7 Arithmetic Logic Shift Unit
Problems
References
CHAPTER FIVE Basic Computer Organization and Design
5-1 Instruction Codes
Stored Program Organization
Indirect Address
5-2 Computer registers
Common Bus System
5-3 Computer Imstructions
Instruction Set Completeness
5-4 Timing and Control
5-5 Instruction Cycle
Fetch and Decode
Determine the Type of Instruction
Register-Reference Instructions
5-6 Memory-Reference Instructions
AND to AC
ADD to AC
LDA:Load to AC
STA: Store AC
BUN:Branch Unconditionally
BSA:Rranch and Save return Address
ISZ:Increment and Skip If Zero
Control Flowchart
5-7 Input-Output and Interrupt
Input-Output Configuration
Input-Output Instructions
Program Interrupt
Imterrupt Cycle
5-8 Complete Computer Description
5-9 Design of Basic Computer
Control Logic Gates
Control of Registers and Memory
Control of Single Flip-Flops
Control of Common Bus
5-10 Design of Accumulator Logic
Control of AC Register
Adder and Logic Circuit
Problems
References
CHAPTER SIX Programming the Basic Computer
6-1 Introduction
6-2 Machine Language
6-3 Assembly Language
Rules of the Language
An Example
Translation to Binary
6-4 The Assembler
Representation of Symbolic Program in Memory
First Pass
Second Pass
6-5 Program Loops
6-6 Programming Arithmetic and Logic Operations
Multiplication Program
Double-Precision Addition
Logic Operations
Shift Operations
6-7 Subroutines
Subroutines Parameters and Data Linkage
6-8 Input-Output Programming
Character Manipulation
Program Interrupt
Problems
References
CHAPTER SEVEN Microprogrammed Control
7-1 Control Memory
7-2 Address Sequencing
Conditional Branching
Mapping of Instruction
Subroutines
7-3 Microprogram Example
Computer Configuration
Microinstruction Format
Symbolic MicroinstructionS
The Fetch Routine
Symbolic Microprogram
Binary Microprogram
7-4 Design of Control Unit
Microprogram Sequencer
Probolems
References
CHAPTER EIGHT Central Processing Unit
8-1 Introduction
8-2 General Register Organization
Control Word
Examples of Microoperations
8-3 Stack Organization
Register Stack
Memory Stack
Reverse Polish Notation
Evaluation of Arithmetic Expressions
8-4 Instruction Formats
Three-Address Instructions
Two-Address Instructions
One-Address Instructions
Zero-Address Instructions
RISC Instructions
8-5 Addressing Modes
Numerical Example
8-6 Data Transfer and Manipulation
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
8-7 Program Control
Status Bit Conditions
Conditional Branch Instructions
Subroutine Call and Retum
Program Interrupt
Types of Interrupts
8-8 Reduced Instruction Set Computer(RISC)
CISC Characteristics
RISC Characteristics
Overlapped Register Windows
Berkeley RISC I
Problems
References
CHAPTER NINE Pipeline and Vector Processing
9-1 Parallel Processing
9-2 Pipelining
General Considerations
9-3 Arithmetic Pipeline
9-4 Instruction Pipeline
Example:Four-Segment Instruction Pipline
Data Dependency
Handing of Branch Instructions
9-5 RISC Pipeline
Example:Three-Segment Instruction Pipeline
Delayed Load
Delayed Branch
9-6 Vector Processing
Vector Operations
Matrix Multiplcation
Memory Interleaving
Supercomputers
9-7 Array Processors
Attached Array Processor
SIMD Array Processor
Problems
References
CHAPTER TEN Computer Arithmetic
10-1 Introduction
10-2 Addition and Subtraction
Addition and Subtraction with Signed-Magnitude Data
Hardware Implementation
Hardware Algorithm
Addition and Subtraction with Signed-2’s Complement Data
10-3 Multiplication Algorithms
Hardware Algorithm
Array Multiplier
10-4 Division Algorithms
Hardware Implementation for Signed-Magnitude Data
Divide Overflow
Hardware Algorithm
Other Algorithms
10-5 Floating-Point Arithmetic Operations
Basic Considerations
Register Considerations
Addition and Subtraction
Multiplication
Division
10-6 Decimal Arithmetic Unit
BCD Adder
BCD Subtraction
10-7 Decimal Arithmetic Operations
Addition and Subtraction
Multiplication
Division
Floating-Point Operations
Problems
References
CHAPTER ELEVEN Input-Output Organization
11-1 Peripheral Devices
ASCII Alphanumeric Characters
11-2 Input-Output Interface
I/O Bus and Interface Modules
I/O versus Memory Bus
Isolated versus Memory-Mapped I/O
Example of I/O Interface
11-3 Asynchronous Data Transfer
Strobe Control
Handshaking
Asynchronous Serial Transfer
Asynchronous Communication Interface
First-In,First-Out Buffer
11-4 Modes of Transfer
Example of Programmed I/O
Interrupt-Initiated I/O
Software Considerations
11-5 Priority Interrupt
Daisy-Chaining Priority
Parallel Priority Interrupt
Priority Encoder
Interrupt Cycle
Software Routines
Initial and Final Operations
11-6 Direct Memory Access(DMA)
DMA Controller
DMA Transfer
11-7 Input-Output PROCessor(IOP)
CPU-IOP Communication
IBM 370 I/O Channel
Intel 8089 IOP
11-8 Serial Communication
Character-Oriented Protocol
Transmission Example
Data Transparency
Bit-Oriented Protocol
Problems
References
CHAPTER TWELVE Memory Organization
12-1 Memory Hierarchy
12-2 Main Memory
RAM and ROM Chips
Memory Address Map
Memory Connecton to CPU
12-3 Auxiliary Memory
Magnetic Disks
Magnetic Tape
12-4 Associative Memory
Hardware Organization
Match Logic
Read Operation
Write Operation
12-5 Cache Memory
Associative Mapping
Direct Mapping
Set-Associative Mapping
Writing into Cache
Cache Initialization
12-6 Virtual Memory
Address Space and Memory Space
Address Mapping Using Pages
Associative Memory Page Table
Page Replacement
12-7 Memory Management Hardware
Segmented-Page Mapping
Numerical Example
Memory Protection
Problems
References
CHAPTER THIRTEEN Multiprocessors
13-1 Characteristics of Multiprocessors
13-2 Interconnection Structures
Time-Shared Common Bus
Multiport Memory
Crossbar Switch
Multistage Switching Network
Hypercube Interconnection
13-3 Interprocessor Arbitration
System Bus
Serial Arbitration Procedure
Parallel Arbitration Logic
Dynamic Arbitration Algorithms
13-4 Interprocessor Communication and Synchronization
Interprocessor Synchronization
Mutual Exclusion with a Semaphore
13-5 Cache Coherence
Conditions for Incoherence
Solutions to the Cache Coherence Problem
Problems
References
Index
