中文名: 电子设计自动化工具
英文名: SynaptiCAD Product Suite
资源格式: 压缩包
版本: V14
发行时间: 2009年
制作发行: SYNAPTICAD INC.
地区: 美国
语言: 英文
简介:
官方网站 http://www.syncad.com/index.htm
SynaptiCAD 公司出品的 EDA（电子设计自动化）工具集合，包括HDL输入、仿真、测试、波形分析、管脚映射工具等等,是一个很完整的EDA方案。
SynaptiCAD Product Suite 由电机工程师创造设计的一款电子互动设计工具，这个互动概念贯穿于所有的接口。您可以开始分析和模拟设计理念，毋须经完成整个电路模型或示意图，帮助工程师他们的设计进行批判性的审视。
SynaptiCAD Product Suite 包含了9种功能强大的工具：
1.TestBencher Pro：
用于从独立于语言的时序逻辑表生成交互式VHDL,Verilog, OpenVera,e, 和TestBuilder 测试基准及总线功能的模型。生成的测试基准能提供基于仿真相应的不同的激发向量，以便于测试基准功能作为一个被测试系统环境的动作模型正常工作。TestBencher Pro是一个优秀的测试大规模FPGA 和 ASIC设计的工具。
2.BugHunter Pro：
一款用于 Verilog， VHDL 和 C++ 模拟器的图形调试系统。BugHunter 支持所有主要的 HDL 模拟器，其主要功能包括：单一步骤调试、波形数据串流、项目管理等等。可以侦测程序与帮助系统的交互过程从而发现问题所在。
3.VeriLogger Pro：
Verilog模拟器软件。提供一个综合了传统Verilog模拟器所有特征的仿真环境，它具有强大的图形测试矢量产生器。VeriLogger的快速模型测试使用户可以对设计中的每个模型进行“自底向上”的测试。
4.WaveFormer Pro：
由时序图分析器、模拟器和测试向量生成器组合而成。它为设计人员提供了一个集成的环境，可以用来开发数字和模拟线路的时序图。WaveFormer Pro可以由Spice模拟器，Mathematica，或Matlab等工具输入模拟数据。还可以利用WaveFormer Pro 内部拥有的波形函数直接生成模拟信号；或者将从总线上得到的数字信号变换成模拟信号。还可以将模拟信号波形逐段线性地变换成Spice模拟器的电压信号源。
5.SimuTAG：
一款功能强大和实时地查证出 FPGAs 的错误的系统。可经由比较FPGA 功能规则反证RTL样式模拟规则，迅速发现逻辑和综合错误。
6.PinPort：
提供数字硬件与Verilog 或C++的虚拟接口环境。
7.DataSheet Pro：
时间表文件夹管理工具。
8.Timing Diagrammer Pro：
时间表设计工具。
9.Gigawave Viewer：
波形观测器。
SynaptiCAD was founded by electrical engineers to create design tools that helped engineers think critically about their designs. Being engineers themselves, they were frustrated by having to almost complete a design before being able to get simulation results. Our founders decided that there must be a better approach for interacting with design tools and from this simple idea they created SynaptiCAD, a company that creates "tools for the thinking mind". This idea permeates all of our tool interfaces. With SynaptiCAD's tools you are able to begin analyzing and simulating design ideas right away without having to complete an entire circuit model or schematic. Our tools automatically handle many of the minor details involved in the design effort, leaving you more time to focus on the bigger picture.
SynaptiCAD based of the electrical engineers, in order to manufacture draft tools, which helped engineers to think of their drafts critically. Being implements blank, it frustrated, by a draft before in the situation its locks nearly must, results of simulation receive. Our founders decided that there must be a better approach for the effect on draft tools and from this simple idea it SynaptiCAD caused, a company, which manufactures tools for the thinking understanding. This idea penetrates all our tool tools. With SynaptiCADs tools in the position you are draft to analyze and to simulate begin ideas immediately to lock without having, an entire electric circuit model or - diagram. Our tools treat automatically many of the small details, those into the draft effort along and leave to you more time to concentrate in the larger illustration.
OS: Windows 2000/XP/Vista
======================================================
[安全检测]
已通过安全检测
安全检测软件：BitDefender Total Security
版本：2009
病毒库发布时间：更新到即时
[安装测试]
未经过安装测试，使用者后果自负与本论坛无关
[免责声明]
该下载内容仅限於个人测试学习之用，不得用於商业用途，并且请在下载后24小时内删除。
软件破解及注册机被杀毒软件报病毒或间谍木马，请自行甄别和取舍，不另行加以解释。
资源版权归作者及其公司所有，如果你喜欢，请购买正版。
====================================
本资源谢绝迅雷、脱兔、vagaa等吸血客户端用户下载，使用以上客户端可能无法联接到本资源下载！VeryCD版电驴等GPL许可的正规emule用户请移步至http://board.VeryCD.com/t473571.html了解反吸血插件，或点此直接下载。
代码
? ?
哌哌哌哌哌哌哌苘苘苘苘苘苘苘苘苘苘苘圹圮苘苘苘苘苘苘苘苘苘苘苓哌哌哌哌哌哌?
苘苒圻圹圮苘?
苒圹哌哌鄄圻哌咣圹?
圹? 安 郯?舶 咣?
咣苘 圹? ?郯?? 槽? 苘苘苘苘 ? 苓
苘膊膊苘? 苘苘苘? 捋? 苘?圮? 圹? 苘槽哌甙安膊圹苘苘?
? 哌北策? 圹? 苒咣苘苘苒咣? 槽? 哌?
圹? 圹圹圹圹圹圹圹? 佰?
苒咣?圹?圹苒圹圹圹圹圹苒?佰?苒咣?
捱圹圹苒鄄圹苒圹圹圹圹圹圹苒鄄圹苒圹圻?
捃鄄圹咣圹郾圹圹圹圹圹圹圹郾圹圹咣鄄圮?
咣苒? 圹?圹圹圹圹圹圹圹?圹? 咣苒?
哌圹圹圹圹圹圹圹圹圻? ? 哕
? ? 圮 鄄
? ? ? ? ? 圹
哌哌 哌哌 槽?槽?
苘 圹?圹鄄
苘? ?苘哌 ? 脖苘 咣?苒圹?
哌哌苘苘苘苘苘苘苒苘 咣圹 ?? 苒鄄
懿圹圹哌哌 ? 膊败? ? 苒圹?
苘?圹圹圹圻哕苘 哌圹圹 苒圻?
哌 苒苘圮 ? 哌?
苘苘? 苘苘? 苘苘? 苘苘? 苒 苘
槽圹咣圹? 槽圹哌圹舶 苒圹哌圹鄄 槽圹哌圹鄄 膊圹 槽圹
鞍 圹圹 圹鄄 佰圹? 苒圹?佰圹? 圹圹 圹鄄苘苘苘? 槽圹 鞍
圹圹 佰圹? 圹圹圹? 佰圹? 哌? 圹圹 佰圹? 槽圹 槽圹
?苒圹圮圹圻 圹圹 苘苘苘苒圹? 槽圹哌圹圹 佰圹? 槽圹 槽圹 苘苘苘 ?
圹圹咣圹? 咣圹苘圹圹 佰圹圮苒圹? 圹圹苘圹鄄 槽圹鞍安圹? 圹鄄
哌哌 咣圹?安哌哌卟? 哌哌哌哌 哌哌哌哌 哌哌哌哌哌哌哌哌? zk.
咣鄄 懿?
? ? 圮 苘苘苘苘苘苘苘苘苘苘苘苘苘苘苘?
苘苘? 苒圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄?
败 懿氨槽圹圹舶郯圹圹圹圹槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹?
槽 苒圹圹槽郯槽圹圹圹圹佰圹圻咣哌圹哌哌哌哌哌圹哌哌圻圹哌哌圹鄄
苒苒苘苘苘苘苘圹曹苘苘懿郯槽苘圮苘苒败脖佰圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄
安圹圹圹圹圹圹圹圹圹圹圹圹鄄圹圹圹圹圹圹郯圹圻哌哌哌哌哌圹圹圹圹圹圹圹圹圹圹?
哌苘苘苘苘苓脖败苘苘圹郯咣圹圹圹圹圹鄄圹?鞍鞍鞍鞍败圹圹咣圹圹圹圹圹圹圹?
甙膊哌哌哌槽圹策 哌哌哌哌咣圹圹圹苒圹圮圹圹圹圹咣舶
哌 甙鞍膊苘脖懿 ? ?咣圹圹鄄
佰鄄圹圹圹?? ? 槽圹圹鄄
槽圹圹圹鄄? 哕苘苓 圹圹圹圹
圹槽鄄圹圹? 圹圹圹圹
槽圹圹圹鄄? 槽圹圹鄄
槽郯圹槽鄄鄄 槽圹圹?
槽郯圹槽鄄鄄 槽圹鄄
苒郯圹郯圹圹? 哌哌?
苘圹佰圹佰鄄圹?
圹圹槽圹佰鄄圹圻
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪 咣圹鄄圹槽圹? 哪哪哪哪哪哪哪哪哪哪哪??
安圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄鞍 咣圹圹圻? 鞍槽圹圹圹圹圹圹圹圹圹舶
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪 ? 哌葸 哪哪哪哪哪哪哪哪哪哪哪哪哪??
? ?
?苒圹鄄曹苘 ? ? [ MOST PROUDLY PRESENTS ] ? ?苘懿槽圹圮 ?
槽? 槽?
? ?
? ?
Product Suite v14.00a
(c) SynaptiCAD
Supplier . : RECOiL Size ..... : 19 x 5.00MB
Cracker .. : RECOiL Protection : FlexLM
Packager . : RECOiL Type ..... : CAD
Date ..... : 05-15-2009 OS ....... : WinALL
? ?
? ?
槽? 槽?
?膊圹圹膊苘?? ? ? ?苘懿槽圹膊??
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
安圹圹圹圹圹圹圹圹圹圹鄄? [ RELEASE NOTES ] 安圹圹圹圹圹圹圹圹圹圹圹舶
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
SynaptiCAD now offers the V2V command line tools for automatic
translation of HDL source code.
Want a powerful, yet easy to use simulation environment? SynaptiCAD's
simulation and debugging tools provide a standard interface for
controlling all of your simulation tools.
SynaptiCAD's timing diagram editors have the most extensive and accurate
timing analysis features available in any timing diagram editor on the
market including delay correlation, reconvergent fan-out, and clocks
that model jitter and buffer delays. Three different levels of editing
let you pick the best price and feature set for your
application.
Free yourself from the time-consuming process of manually writing
Verilog, VHDL, and SystemC test benches. Generate them graphically from
timing diagrams. SynaptiCAD provides 3 levels of test bench generation
to meet all your design needs.
SynaptiCAD offers support for the latest test equipment and emulation
technologies allowing you to port your simulation and timing analysis
data to your prototyping environment.
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
安圹圹圹圹圹圹圹圹圹圹鄄? [ INSTALLATION ] 安圹圹圹圹圹圹圹圹圹圹圹舶
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
Unzip , Unrar. Check /crack dir. Enjoy!
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
安圹圹圹圹圹圹圹圹圹圹鄄? [ GROUP iNFO ] 安圹圹圹圹圹圹圹圹圹圹圹舶
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
We are not taking any applications. We are an invite only group.
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
安圹圹圹圹圹圹圹圹圹圹鄄? [ GREETINGS ] 安圹圹圹圹圹圹圹圹圹圹圹舶
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
Our friends, our loyal members and our fair competitors.
You know who you are.
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
安圹圹圹圹圹圹舶 [ RECOiL IN 2009 - ONE MORE IMPACT! ] 安圹圹圹圹圹圹舶
?哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪??
