智能存储系统 Intelligent memory systems
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作者： Frederic T. Chong著
出 版 社： 湖南文艺出版社
出版时间： 2002-12-1字数：版次： 1页数： 190印刷时间： 2001/12/01开本：印次：纸张： 胶版纸I S B N ： 9783540423287包装： 平装编辑推荐
The LNCS series reports state-of-the-art results in computer science research, development, and education, at a high level and in both printed and electronic form. Enjoying tight cooperation with the R&D community, with numerous individuals, as well as with prestigious organizations and societies, LNCS has grown into the most comprehensive computer science resarch forum available.
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-proceedings(published in time for the respective conference)
-post-proceedings(consisting of thoroughly revised final full papers)
-research monographs(which may be basde on outstanding PhD work, research projects, technical reports, etc.)
内容简介
This book presents the thoroughly refereed post-proceedings of the Second International Workshop on Intelligent Memory Systems, IMS 2000, held in Cambridge, MA, USA, in November 2000.The nine revised full papers and six poster papers presented were carefully reviewed and selected from 28 submissions. The papers cover a wide range of topics in intelligent memory computing; they are organized in topical sections on memory technology, processor and memory architecture, applications and operating systems, and compiler technology.
目录
Memory Technology
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
Software Controlled Reconfigurable On-Chip Memoryfor High Performance Computing
Processor and Memory Architecture
Content-Based Prefetching: Initial Resul
Memory System Support for Dynamic Cache Line Assembly
Adaptively Mapping Code in an Intelligent Memory Architecture
Applications and Operating Systems
The Characterization of Date Intensive Memory Workloadson Distributed PIM Systems
Memory Management in a PIM-Based Architecture
Compiler Technology
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
FlexCache: A Framework for Flexible Compiler Generated Data Caching
Poster Session
Aggressive Memory-Aware Compilation
Energy/Performance Design of Memory Hierarchiesfor Processor-in-Memory Chips
SAGE: A New Analysis and Optimization System for FlexRAM Architecture
Performance/Energy Efficiency of Variable Line-Size Cachesfor Intelligent Memory Systems
The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
Compiler-Directed Cache Line Size Adaptivity
Workshop Notes
Author Index
